dig7seg

cesars/3-digit-multiplex-7seg/dig7seg

No description
dig7seg
@/dig7seg
SEGAport
Board port to write to
SEGBport
Board port to write to
SEGCport
Board port to write to
SEGDport
Board port to write to
SEGEport
Board port to write to
SEGFport
Board port to write to
SEGGport
Board port to write to
INnumber
ENboolean
State to write
UPDpulse
Triggers new write
dig7seg
SEGA
SEGB
SEGC
SEGD
SEGE
SEGF
SEGG
IN
EN
UPD
DONE
ERR
ERRpulse
Fires if write failed. E.g. `PORT` does not exist.
DONEpulse
Fires on writing complete
To use the node in your project you should have the cesars/3-digit-multiplex-7seg library installed. Use the “File → Add Library” menu item in XOD IDE if you don’t have it yet. See Using libraries for more info.

C++ implementation

struct State {
};

{{ GENERATED_CODE }}

void evaluate(Context ctx) {
    if (!isInputDirty<input_UPD>(ctx))
        return;

    const uint8_t portA = getValue<input_SEGA>(ctx);
    const uint8_t portB = getValue<input_SEGB>(ctx);
    const uint8_t portC = getValue<input_SEGC>(ctx);
    const uint8_t portD = getValue<input_SEGD>(ctx);
    const uint8_t portE = getValue<input_SEGE>(ctx);
    const uint8_t portF = getValue<input_SEGF>(ctx);
    const uint8_t portG = getValue<input_SEGG>(ctx);

    if (!isValidDigitalPort(portA) || !isValidDigitalPort(portB) || !isValidDigitalPort(portC) || 
        !isValidDigitalPort(portD) || !isValidDigitalPort(portE) || !isValidDigitalPort(portF) || !isValidDigitalPort(portG)) {
        emitValue<output_ERR>(ctx, 1);
        return;
    }

    ::pinMode(portA, OUTPUT);
    ::pinMode(portB, OUTPUT);
    ::pinMode(portC, OUTPUT);
    ::pinMode(portD, OUTPUT);
    ::pinMode(portE, OUTPUT);
    ::pinMode(portF, OUTPUT);
    ::pinMode(portG, OUTPUT);

    int num = getValue<input_IN>(ctx);
	bool val = getValue<input_EN>(ctx);

 switch (num){
        case 1:
    ::digitalWrite(portA, 0);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, 0);
    ::digitalWrite(portE, 0);
    ::digitalWrite(portF, 0);
    ::digitalWrite(portG, 0);
    break;
        case 2:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, 0);
    ::digitalWrite(portD, val);
    ::digitalWrite(portE, val);
    ::digitalWrite(portF, 0);
    ::digitalWrite(portG, val);
    break;
        case 3:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, val);
    ::digitalWrite(portE, 0);
    ::digitalWrite(portF, 0);
    ::digitalWrite(portG, val);
    break;
        case 4:
    ::digitalWrite(portA, 0);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, 0);
    ::digitalWrite(portE, 0);
    ::digitalWrite(portF, val);
    ::digitalWrite(portG, val);
    break;
        case 5:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, 0);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, val);
    ::digitalWrite(portE, 0);
    ::digitalWrite(portF, val);
    ::digitalWrite(portG, val);
    break;
        case 6:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, 0);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, val);
    ::digitalWrite(portE, val);
    ::digitalWrite(portF, val);
    ::digitalWrite(portG, val);
    break;
        case 7:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, 0);
    ::digitalWrite(portE, 0);
    ::digitalWrite(portF, 0);
    ::digitalWrite(portG, 0);
    break;
        case 8:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, val);
    ::digitalWrite(portE, val);
    ::digitalWrite(portF, val);
    ::digitalWrite(portG, val);
    break;
        case 9:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, val);
    ::digitalWrite(portE, 0);
    ::digitalWrite(portF, val);
    ::digitalWrite(portG, val);
    break;
    default:
    ::digitalWrite(portA, val);
    ::digitalWrite(portB, val);
    ::digitalWrite(portC, val);
    ::digitalWrite(portD, val);
    ::digitalWrite(portE, val);
    ::digitalWrite(portF, val);
    ::digitalWrite(portG, 0);
 }
    emitValue<output_DONE>(ctx, 1);
}